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dual bootstrapped 12 v mosfet driver with output disable adp3120 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features all-in-one synchronous buck driver bootstrapped high-side drive one pwm signal generates both drives anticross-conduction protection circuitry output disable control turns off both mosfets to float output per intel? vrm 10 specification applications multiphase desktop cpu supplies single-supply synchronous buck converters general description the adp3120 is a dual, high voltage mosfet driver optimized for driving two n-channel mosfets, the two switches in a non- isolated synchronous buck power converter. each of the drivers is capable of driving a 3000 pf load with a 45 ns propagation delay and a 25 ns transition time. one of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. the adp3120 includes overlapping drive protection to prevent shoot-through current in the external mosfets. the od pin shuts off both the high-side and the low-side mosfets to prevent rapid output capacitor discharge during system shutdown. the adp3120 is specified over the commercial temperature range of 0c to 85c and is available in 8-lead soic and 8-lead lfcsp packages. simplified functional block diagram 2 3 od in adp3120 vcc bst drvh sw drvl pgnd delay vcc 6 delay cmp cmp 1v 4 1 7 control logic 6 5 8 r bst r g c bst1 d1 c bst2 12v q1 to inductor q2 05591-001 figure 1. obsolete
adp3120 rev. 0 | page 2 of 16 table of contents specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configurations and function descriptions ........................... 5 timing characteristics ..................................................................... 6 typical performance characteristics ............................................. 7 theory of operation ........................................................................ 9 low-side driver ............................................................................ 9 high-side driver .......................................................................... 9 overlap protection circuit .......................................................... 9 application information ................................................................ 10 supply capacitor selection ....................................................... 10 bootstrap circuit ........................................................................ 10 mosfet selection ..................................................................... 10 high-side (control) mosfets ................................................ 10 low-side (synchronous) mosfets ........................................ 11 pc board layout considerations ............................................. 11 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision history 7/05revision 0: initial version obsolete
adp3120 rev. 0 | page 3 of 16 specifications 1 vcc = 12 v, bst = 4 v to 26 v, t a = 0c to 85c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit pwm input input voltage high 2.0 v input voltage low 0.8 v input current ?1 +1 a hysteresis 90 250 mv od input input voltage high 2.0 v input voltage low 0.8 v input current ?1 +1 a hysteresis 90 250 mv propagation delay times 2 odpdhl t see figure 4 20 35 ns odpdhl t see figure 4 40 55 ns high-side driver output resistance, sourcing current bst ? sw = 12 v 2.2 3.5 output resistance, sinking current bst C sw = 12 v 1.0 2.5 output resistance, unbiased bst C sw = 0 v 10 k transition times t rdrvh bst C sw = 12 v, c load = 3 nf, see figure 5 25 40 ns t fdrvh bst C sw = 12 v, c load = 3 nf, see figure 5 20 30 ns propagation delay times 2 t pdhdrvh bst C sw = 12 v, c load = 3 nf, 25c t a 85c, see figure 5 32 45 70 ns t pdldrvh bst C sw = 12 v, c load = 3 nf, see figure 5 25 35 ns sw pull-down resistance sw to pgnd 10 k low-side driver output resistance, sourcing current 2.0 3.2 output resistance, sinking current 1.0 2.5 output resistance, unbiased vcc = pgnd 10 k transition times t rdrvl c load = 3 nf, figure 5 20 35 ns t fdrvl c load = 3 nf, figure 5 16 30 ns propagation delay times 2 t pdhdrvl c load = 3 nf, figure 5 12 35 ns t pdldrvl c load = 3 nf, figure 5 30 45 ns timeout delay sw = 5 v 110 190 ns sw = pgnd 95 150 ns supply supply voltage range vcc 4.15 13.2 v supply current i sys bst = 12 v, in = 0 v 2 5 ma uvlo voltage vcc rising 1.5 3.0 v hysteresis 350 mv 1 all limits at temperature extremes are gua ranteed via correlation using standard st atistical quality control (sqc) methods. 2 for propagation delays, t pdh refers to the specified signal going high, and t pdl refers to it going low. obsolete
adp3120 rev. 0 | page 4 of 16 absolute maximum ratings table 2. parameter rating vcc C0.3 v to +15 v bst C0.3 v to vcc +15 v bst to sw C0.3 v to +15 v sw dc C5 v to +15 v <200 ns C10 v to +25 v drvh dc sw C 0.3 v to bst + 0.3 v <200 ns sw C 2 v to bst + 0.3 v drvl dc C0.3 v to vcc + 0.3 v <200 ns C2 v to vcc + 0.3 v in, od C0.3 v to 6.5 v ja , soic 2-layer board 123c/w 4-layer board 90c/w ja , lfcsp 1 4-layer board 50c/w operating ambient temperature range 0c to 85c junction temperature range 0c to 150c storage temperature range C65c to +150c lead temperature range soldering (10 sec) vapor phase (60 sec) infrared (15 sec) 300c 215c 260c 1 for lfcsp, ja is measured per jedec std with exposed pad soldered to pcb. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. unless otherwise specified, all voltages are referenced to pgnd. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. obsolete
adp3120 rev. 0 | page 5 of 16 pin configurations and function descriptions bst 1 in 2 od 3 v cc 4 drvh 8 sw 7 pgnd 6 drvl 5 adp3120 top view (not to scale) 05591-002 figure 2. 8-lead soic pin configuration pin 1 indicator 1bst 2in 3od 4vcc 7sw 8 drvh 6 pgnd 5 drvl top view (not to scale) adp3120 05591-003 figure 3. 8-lead lfcsp pin configuration table 3. pin function descriptions pin o. neonic description 1 bst upper mosfet floating bootstrap supply. a capacitor connected between the bst and sw pins holds this bootstrapped voltage for the high-s ide mosfet as it is switched. 2 in logic level pwm input. this pin has primary control of th e drive outputs. in normal operation, pulling this pin low turns on the low-side driver; pulling it high turns on the high-side driver. 3 od output disable. when low, this pin disables normal operation, forcing drvh and drvl low. 4 vcc input supply. this pin should be bypassed to pgnd with an ~1 f ceramic capacitor. 5 drvl synchronous rectifier drive. output drive for the lower (synchrono us rectifier) mosfet. 6 pgnd power ground. should be closely conne cted to the source of the lower mosfet. 7 sw this pin is connected to the buck-switching node, close to the upper mosfet source. it is the floating return for the upper mosfet drive signal. it is also used to monitor the switched voltage to prevent the lower mosfet from turning on until the voltage is below ~1 v. 8 drvh buck drive. output dri ve for the upper (buck) mosfet. obsolete
adp3120 rev. 0 | page 6 of 16 timing characteristics tpdl od 90% 10% od drvh or drvl tpdh od 05591-004 figure 4. output disable timing diagram in drvh-sw drvl sw tpdl drvl tf drvl tr drvl tpdl drvh tf drvh tpdh drvh tr drvh v th v th 1v tpdh drvl 05591-005 figure 5. timing diagram (timing is referenced to the 90% and 10% points, unless otherwise noted.) obsolete
adp3120 rev. 0 | page 7 of 16 typical performance characteristics 05591-006 drvh drvl in figure 6. drvh rise and drvl fall times c load = 6 nf for drvl, c load = 2 nf for drvh 05591-007 drvh drvl vin figure 7. drvh fall and drvl rise times c load = 6 nf for drvl, c load = 2 nf for drvh 35 15 0 125 05591-008 junction temperature ( c) rise time (ns) 30 25 20 25 50 75 100 drvl drvh vcc = 12v c load = 3nf figure 8. drvh and drvl rise times vs. temperature 24 14 0 125 05591-009 junction temperature ( c) fall time (ns) 22 20 18 16 25 50 75 100 drvl drvh vcc = 12v c load = 3nf figure 9. drvh and drvl fall times vs. temperature 40 5 2.0 5.0 05591-010 load capacitance (nf) rise time (ns) 35 30 25 20 15 10 2.5 3.0 3.5 4.0 4.5 t a = 25 c vcc = 12v drvh drvl figure 10. drvh and drvl rise times vs. load capacitance 35 5 2.0 5.0 05591-011 load capacitance (nf) fall time (ns) 30 25 20 15 10 2.5 3.0 3.5 4.0 4.5 vcc = 12v t a = 25 c drvh drvl figure 11. drvh and drvl fall times vs. load capacitance obsolete
adp3120 rev. 0 | page 8 of 16 60 0 0 05591-012 frequency (khz) supply current (i cc [ma]) 45 30 15 200 400 600 800 1000 1200 1400 t a = 25 c vcc = 12v c load = 3nf figure 12. supply current vs. frequency 13 9 0 125 05591-013 junction temperature ( c) supply current (ma) 12 11 10 25 50 75 100 vcc = 12v c load = 3nf f in = 250khz figure 13. supply current vs. temperature 12 0 01 05591-014 vcc (v) drvl output voltage (v) 2 11 10 9 8 7 6 5 4 3 2 1 1234567891011 t a = 25 c c load = 3nf figure 14. drvl output voltage vs. supply voltage obsolete
adp3120 rev. 0 | page 9 of 16 theory of operation the adp3120 is optimized for driving two n-channel mosfets in a synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high-side and the low-side mosfets. each driver is capable of driving a 3 nf load at speeds up to 500 khz. a more detailed description of the adp3120 and its features follows. see figure 1 . low-side driver the low-side driver is designed to drive a ground-referenced n-channel mosfet. the bias to the low-side driver is internally connected to the vcc supply and pgnd. when the driver is enabled, the drivers output is 180 out of phase with the pwm input. when the adp3120 is disabled, the low-side gate is held low. high-side driver the high-side driver is designed to drive a floating n-channel mosfet. the bias voltage for the high-side driver is developed by an external bootstrap supply circuit, which is connected between the bst and sw pins. the bootstrap circuit comprises a diode, d1, and bootstrap capacitor, c bst1 . c bst2 and r bst are included to reduce the high- side gate drive voltage and to limit the switch node slew rate (called a boot-snap circuitsee the application information section for more details). when the adp3120 starts up, the sw pin is at ground, so the bootstrap capacitor charges up to vcc through d1. when the pwm input goes high, the high-side driver begins to turn on the high-side mosfet, q1, by pulling charge out of c bst1 and c bst2 . as q1 turns on, the sw pin rises up to v in , forcing the bst pin to v in + v c(bst) , which is enough gate-to-source voltage to hold q1 on. to complete the cycle, q1 is switched off by pulling the gate down to the voltage at the sw pin. when the low-side mosfet, q2, turns on, the sw pin is pulled to ground. this allows the bootstrap capacitor to charge up to vcc again. the output of the high-side driver is in phase with the pwm input. when the driver is disabled, the high-side gate is held low. overlap protection circuit the overlap protection circuit prevents both of the main power switches, q1 and q2, from being on at the same time. this is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. the overlap protection circuit accomplishes this by adaptively controlling the delay from the q1 turn off to the q2 turn on, and by internally setting the delay from the q2 turn off to the q1 turn on. to prevent the overlap of the gate drives during the q1 turn off and the q2 turn on, the overlap circuit monitors the voltage at the sw pin. when the pwm input signal goes low, q1 begins to turn off (after propagation delay). before q2 can turn on, the overlap protection circuit makes sure that sw has first gone high and then waits for the voltage at the sw pin to fall from v in to 1 v. once the voltage on the sw pin falls to 1 v, q2 begins turn on. if the sw pin has not gone high first, the q2 turn on is delayed by a fixed 150 ns. by waiting for the voltage on the sw pin to reach 1 v or for the fixed delay time, the overlap protection circuit ensures that q1 is off before q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. if sw does not go below 1 v after 190 ns, drvl turns on. this can occur if the current flowing in the output inductor is negative and is flowing through the high-side mosfet body diode. obsolete
adp3120 rev. 0 | page 10 of 16 application information supply capacitor selection for the supply input (vcc) of the adp3120, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. use a 4.7 f, low esr capacitor. multilayer ceramic chip (mlcc) capacitors provide the best combination of low esr and small size. keep the ceramic capacitor as close as possible to the adp3120. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c bst ) and a diode, as shown in figure 1 . these components can be selected after the high-side mosfet has been chosen. the bootstrap capacitor must have a voltage rating that can handle twice the maximum supply voltage. a minimum 50 v rating is recommended. the capacitor values are determined using the following equations: gate gate bst2 bst1 v q cc =+ 10 (1) d cc gate bst2 bst1 bst1 vv v cc c ? = + (2) where: q gate is the total gate charge of the high-side mosfet at v gate . v gate is the desired gate drive voltage (usually in the range of 5 v to 10 v, 7 v being typical). v d is the voltage drop across d1. rearranging equation 1 and equation 2 to solve for c bst1 yields d cc gate bst1 vv q c ? = 10 c bst2 can then be found by rearranging equation 1: 1 10 bst gate gate bst2 c v q c ?= for example, an ntd60n02 has a total gate charge of about 12 nc at v gate = 7 v. using vcc = 12 v and v d = 1 v, one finds c bst1 = 12 nf and c bst2 = 6.8 nf. good quality ceramic capacitors should be used. r bst is used to limit slew rate and to minimize the ringing at the switch node. it also provides peak current limiting through d1. an r bst value of 1.5 to 2.2 is a good choice. the resistor needs to handle at least 250 mw due to the peak currents that flow through it. a small-signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by vcc. the bootstrap diode must have a minimum 15 v rating to withstand the maximum supply voltage. the average forward current can be estimated by max gate avgf fqi = )( (3) where f max is the maximum switching frequency of the controller. the peak surge current rating should be calculated using bst d cc peakf r vv i ? = )( (4) mosfet selection when interfacing the adp3120 to external mosfets, the designer should consider ways to make a robust design that minimizes stresses on both the driver and the mosfets. these stresses include exceeding the short-time duration voltage ratings on the driver pins as well as the external mosfet. it is also highly recommended to use the boot-snap circuit to improve the interaction of the driver with the characteristics of the mosfets. if a simple bootstrap arrangement is used, make sure to include a proper snubber network on the sw node. high-side (control) mosfets a high-side, high speed mosfet is usually selected to minimize switching losses (see the adp3186 or adp3188 data sheet for flex-mode 1 controller details). this typically implies a low gate resistance and low input capacitance/charge device. yet, a significant source lead inductance can also exist. this depends mainly on the mosfet package; it is best to contact the mosfet vendor for this information. the adp3120 drvh output impedance and the input resistance of the mosfets determine the rate of charge delivery to the internal capacitance of the gate. this determines the speed at which the mosfets turn on and off. however, because of potentially large currents flowing in the mosfets at the on and off times (this current is usually larger at turn off due to ramping up of the output current in the output inductor), the source lead inductance generates a significant voltage when the high-side mosfets switch off. this creates a significant drain-source voltage spike across the internal die of the mosfets and can lead to a catastrophic avalanche. the mechanisms involved in this avalanche condition can be referenced in literature from the mosfet suppliers. 1 flex-mode? is protected by u.s. patent 6683441. obsolete
adp3120 rev. 0 | page 11 of 16 the mosfet vendor should provide a maximum voltage slew rate at drain current rating such that this can be designed around. once this specification is obtained, determine the maximum current expected in the mosfet. this can be done with the following equation: () out max max out cc dc max lf d vvphaseperii ?+ = ) (( 5 ) where: d max is determined for the vr controller being used with the driver. this current is divided roughly equally between mosfets if more than one is used (assume a worst-case mismatch of 30% for design margin). l out is the output inductor value. when producing the design, there is no exact method for calculating the dv/dt due to the parasitic effects in the external mosfets as well as the pcb. however, it can be measured to determine if it is safe. if it appears that the dv/dt is too fast, an optional gate resistor can be added between drvh and the high-side mosfets. this resistor slows down the dv/dt, but it increases the switching losses in the high-side mosfets. the adp3120 has been optimally designed with an internal drive impedance that works with most mosfets to switch them efficiently, yet minimizes dv/dt. however, some high speed mosfets may require this external gate resistor depending on the currents being switched in the mosfet. low-side (synchronous) mosfets the low-side mosfets are usually selected to have a low on resistance to minimize conduction losses. this usually implies a large input gate capacitance and gate charge. the first concern is to make sure the power delivery from the adp3120 drvl does not exceed the thermal rating of the driver (see the adp3186 or adp3188 data sheet for flex-mode controller details). the next concern for the low-side mosfets is to prevent them from being switched on inadvertently when the high-side mosfet turns on. this occurs due to the drain-gate (miller, also specified as c rss ) capacitance of the mosfet. when the drain of the low-side mosfet is switched to vcc by the high- side turning on (at a dv/dt rate ), the internal gate of the low- side mosfet is pulled up by an amount roughly equal to vcc (c rss /c iss ). it is important to make sure this does not put the mosfet into conduction. another consideration is the nonoverlap circuitry of the adp3120, which attempts to minimize the nonoverlap period. during the state of the high-side turning off to low-side turning on, the sw pin is monitored (as well as the conditions of sw prior to switching) to adequately prevent overlap. however, during the low-side turn off to high-side turn on, the sw pin does not contain information for determining the proper switching time, so the state of the drvl pin is monitored to go below one sixth of vcc. then a delay is added. due to the miller capacitance and internal delays of the low- side mosfet gate, one must ensure that the miller-to-input capacitance ratio is low enough and that the low-side mosfet internal delays are not so large as to allow accidental turn on of the low-side when the high-side turns on. contact adi for an updated list of recommended low-side mosfets. pc board layout considerations use these general guidelines when designing printed circuit boards: ? trace out the high current paths and use short, wide (>20 mil) traces to make these connections. ? minimize trace inductance between drvh and drvl outputs and mosfet gates. ? connect the pgnd pin of the adp3120 as closely as possible to the source of the lower mosfet. ? locate the vcc bypass capacitor as close as possible to the vcc and pgnd pins. ? use vias to other layers when possible to maximize thermal conduction away from the ic. the circuit in figure 16 shows how four drivers can be combined with an adp3188 to form a total power conver- sion solution for generating vcc (core) for an intel cpu that is vrd 10.x-compliant. figure 15 shows an example of the typical land patterns based on the guidelines given previously. for more detailed layout guidelines for a complete cpu voltage regulator subsystem, refer to the pc board layout considerations section of the adp3188 data sheet. 05591 -015 d1 c bst2 c bst1 r bst c vcc figure 15. external component placement example obsolete
adp3120 rev. 0 | page 12 of 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d5 1n4148 c19 4.7 f q13 ntd60n02 q15 ntd110n02 q16 ntd110n02 c16 6.8nf c17 4.7 f u5 adp3120 bst 1 in 2 3 vcc 4 drvh sw pgnd drvl 8 7 6 5 l5 320nh/1.4m rth1 100k , 5% ntc r6 2.2 c20 12nf d4 1n4148 c15 4.7 f q9 ntd60n02 q11 ntd110n02 q12 ntd110n02 c14 6.8nf c13 4.7 f u4 adp3120 bst 1 in 2 3 vcc 4 drvh sw pgnd drvl 8 7 6 5 l4 320nh/1.4m r5 2.2 c16 12nf d3 1n4148 c11 4.7 f q5 ntd60n02 q7 ntd110n02 q8 ntd110n02 c10 6.8nf c9 4.7 f u3 adp3120 bst 1 in 2 3 vcc 4 drvh sw pgnd drvl 8 7 6 5 d1 1n4148 l3 320nh/1.4m r4 2.2 c12 12nf d2 1n4148 c7 4.7 f q1 ntd60n02 q3 ntd110n02 q4 ntd110n02 c6 6.8nf c5 4.7 f u2 adp3120 bst 1 in 2 3 vcc 4 drvh sw pgnd drvl 8 7 6 5 l2 320nh/1.4m r3 2.2 c8 12nf + + c24 c31 10 f 18 mlcc in socket v cc (core) 0.8375v ? 1.6v 95a tdc, 119a pk v cc (core) rtn 560 f/4v 8 sanyo sepc series 5m each u1 adp3188 vid4 vid3 vid2 vid1 vid0 vid5 fbrtn fb comp pwrgd en delay rt rampadj vcc pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 gnd cscomp cssum csref ilimit r ph1 158k , 1% r ph2 158k , 1% r ph3 158k , 1% r ph4 158k , 1% r cs2 84.5k c a 470pf c b 470pf r cs1 35.7k r a 12.1k r b 1.21k c cs2 1.5nf c fb 22pf c cs1 560pf c22 1nf r lim 150k , 1% c23 1nf c21 1 1nf power good enable from cpu c ldy 39nf r ldy 470k r t 137k , 1% r2 357k , 1% + c3 100 f c4 1 f ++ c1 c2 l1 370nh 18a 2700 f/16v/3.3a 2 sanyo mv-wx series v in 12v v in rtn 05591-016 od od od od r sw1 1 r sw2 1 r sw3 1 r sw4 1 note: 1. for a description of optional components , see the adp3188 theory of operation section. r1 10 figure 16. vrd 10.x-compliant power supply circuit obsolete
adp3120 rev. 0 | page 13 of 16 outline dimensions 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012-aa figure 17. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters (inches) 1 exposed pad (bottom view) 0.50 bsc 0.60 max pin 1 indicato r 1.50 ref 0.50 0.40 0.30 2.75 bsc sq top view 12 max 0.70 max 0.65 typ seating plane pin 1 indicator 0.90 max 0.85 nom 0.30 0.23 0.18 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 4 1.60 1.45 1.30 3.00 bsc sq 5 8 figure 18. 8-lead lead frame chip scale package [lfcsp_vd] 3 mm x 3 mm body, very thin, dual-lead (cp-8-2) dimensions shown in millimeters ordering guide model temperature range package description package option quantity per reel branding ADP3120JRZ 1 0c to 85c 8-lead standard small outline package (soic_n) r-8 n/a ADP3120JRZ-rl 0c to 85c 8-lead standard sma ll outline package(soic_n) r-8 2500 adp3120jcpz-rl 0c to 85c 8-lead lead frame chip scale package (lfcsp_vd) cp-8-2 2500 l14 1 z = pb-free part. obsolete
adp3120 rev. 0 | page 14 of 16 notes obsolete
adp3120 rev. 0 | page 15 of 16 notes obsolete
adp3120 rev. 0 | page 16 of 16 notes ? 2005 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05591C0C7/05(0) obsolete

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